Tuesday, September 16, 2008

Adding Low Power modes in PXA - P2

Power Modes in PXA

PXA has the following power modes
  • Normal mode
  • Idle mode
  • Deep idle mode
  • Standby mode
  • Sleep mode
  • Deep Sleep mode
Each mode is characterized by the power domains that will be kept active and the clocks that will be running. For example in Sleep mode all the external low voltage power domains (i.e. domains controlled by PWR_EN pin of PXA) is disabled. While on the other hand, in Deep Sleep mode both the external low voltage and high voltage power domains are disabled as both PWR_EN and SYS_EN pins are de-asserted while entering the low power mode. The choice of which power mode to use for each depends solely on the power consumption requirements of the product.

In the beginning of the project, we mapped the Standby mode of PXA to POWER_STATE_SUSPEND state of Windows CE. But as we had a tight power consumption requirement for the Suspend mode, we had to re map the state to Sleep mode of PXA instead of standby.

Transition of Power Modes

For initiating a power mode transition in PXA, we need write in to the coprocessor 14 , register C7 (PWRMODE). Writing the bit pattern for each pattern corresponding to the power mode in to the PWRMODE[M] bits initiates the transition. For eg:

XllpPmEnterDeepSleep FUNCTION

ldr r3, =0x00000007
mcr p14, 0, r3, c7, c0, 0

A call to this assembly routine will initiate a transition to deep sleep mode.

Context Restoration

While going into low power modes such as Sleep or Deep Sleep, the processor contents can get corrupted.

Lets take the example of Sleep mode. In Sleep mode, the PC (Program Counter) value is corrupted along with some other set of registers. So in order to tackle this situation, operating systems are doing a context storage and restoration while going into low power mode. It stores the status of all the required registers such as GPIO configurations, level, stack address, core configuration registers in to a memory area. The address of this memory area is kept in a register which will be retained during the low power mode. In the case of PXA, it is the Power Manager Scratch Pad Register (PSPR). This register value will be maintained during a sleep reset, but will be cleared during GPIO, power on , hardware or watch dog resets.

So while going in to sleep mode, the required information is stored in a data area in RAM and the address to this area is stored in PSPR register. While resuming from sleep mode, the boot loader will check the PSPR register and will restore the configuration that is stored in the data area.

NOTE: bear in mind that the data area is in RAM, so the RAM needs to be properly initialized after a sleep reset, otherwise the boot loader can hand while trying to access the restoration area.